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 Open source IDE for VHDL Hardware Developement based on Eclipse

 Authors:  Guenter Bartsch, Stefan Holst 
 Family:   IDEFamily EclipseFamily
 Platform: Eclipse
 License:  GPL

"Signs" stands for "Simple Gate Net Simulator".

The project goal is to provide a set of tools for gate-level logic synthesis, analysis and simulation, based on a subset of VHDL. This includes gnc, the gate net compiler which understands an easily synthesizable subset of VHDL (but includes behavioural VHDL constructs) and gns, the gate net simulator and analyzer which provides a graphical netlist viewer and an event-based gatelevel simulator. More tools may be added later, especially place+route tools to generate FPGA programming data are planned.


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Last edited February 23, 2011 4:29 pm (diff)